Leistungen der NRP

In today's fast-paced technological landscape, the demand for smart sensors with improved performance and efficiency is ever-increasing. Application-Specific integrated Circuits (ASICs) are custom-designed chips tailored for specific tasks and play a crucial role in this transition. An ASIC with an integrated microcontroller provides processing power, control capabilities and communication interfaces, thereby operating effectively in disparate and complex applications.

In this context, RISC-V has become a standout player, drawing a considerable attention in the last couple of years. RISC-V distinguishes itself by being an open-source architecture, eliminating costs related to licenses and royalties. This, coupled with its inherent flexibility, facilitates seamless customization and optimization across a diverse range of applications. Moreover, RISC-V core-based ASIC design encourages innovation within a dynamic and shared ecosystem. Today, tech giants such as Google are already designing new generation Central Processing Unit (CPU) architectures based on the RISC-V. This statement alone captures the extensive scope and immense potential of a RISC-V architecture.

Despite its prominence in larger-scale and high-performance computing applications, RISC-V is not yet common in industrial sensors ASICs which require mature technologies driven by a combination of precision requirements, reliability considerations and cost effectiveness. Today several 0.18 µm high voltage and analog mixed-signal technologies are matured and have lower prices. This allows considering the design of more complex circuits, including microcontrollers and application-specific coprocessors. To exploit the full potential of the RISC-V technology, industrial partners have to face challenges in hardware-related technical aspects as well as maturity- and security-related concerns about software toolchains.

The goal of this project is to foster a shared understanding among industrial partners about the open-source RISC-V architecture, both in terms of its hardware and the software toolchain ecosystem. The project will focus on low power and low footprint ASIC implementations with a close look at safety and software security aspects. This collaborative knowledge-sharing initiative will enable industrial partners to make informed decisions, promote innovation and drive the adoption of RISC-V architectures into their industrial sensors.

The ERMIIS project will start in January 2024 and end in December 2024.